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com:ai_thinker_products [2026/03/06 21:57] – vamsancom:ai_thinker_products [2026/03/28 16:20] (current) – [RA-01 / RA-02 Pinout] vamsan
Line 62: Line 62:
 ^6|DIO1|I/O|Digital I/O 1 (timeout/other interrupts)| ^6|DIO1|I/O|Digital I/O 1 (timeout/other interrupts)|
 ^7|DIO2|I/O|Digital I/O 2 (FHSS/other interrupts)| ^7|DIO2|I/O|Digital I/O 2 (FHSS/other interrupts)|
-^8|DIO3|I/O|Digital I/O 3| +^8|DIO3|I/O|Digital I/O 3 CAD/Header (Channel Activity Detection)| 
-^9|DIO4|I/O|Digital I/O 4| +^9|DIO4|I/O|Digital I/O 4 Preamble/Ready| 
-^10|DIO5|I/O|Digital I/O 5|+^10|DIO5|I/O|Digital I/O 5 System Ready / ModeReady signaling|
 ^11|SCK|SPI|SPI Serial Clock| ^11|SCK|SPI|SPI Serial Clock|
 ^12|MISO|SPI|SPI Master In Slave Out| ^12|MISO|SPI|SPI Master In Slave Out|
Line 71: Line 71:
 ^15|GND|Power|Ground| ^15|GND|Power|Ground|
 ^16|GND|Power|Ground| ^16|GND|Power|Ground|
 +
 +**DIO Functionality in LoRa Mode**
 +
 +^Pin^Default/Common Function^Detailed Events|
 +^DIO0|RX/TX Done|Signals //RxDone// (packet received) or //TxDone// (packet sent).|
 +^DIO1|Timeout|Signals //RxTimeout//, //FhssChangeChannel//, or //CadDetected//.|
 +^DIO2|FHSS/Payload|Signals //FhssChangeChannel// or //FhssValidHeader// (frequency hopping).|
 +^DIO3|CAD/Header|Signals //CadDone//, //ValidHeader//, or //PayloadCrcError//.|
 +^DIO4|Preamble/Ready|Signals //PreambleDetect//, //ModeReady//, or //PllLock//.|
 +^DIO5|System Ready|Signals //ModeReady//, //ClkOut//, or //PllLock//.|
  
 **Important Wiring Notes** **Important Wiring Notes**